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582: Can't Render, Fog It
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Spatial personas in the Vision Pro, how to buy a car, how to charge a car, and how not to make cars.
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@atpfm The reticle limit is not specific to TSMC. Reticles (the physical glass/quartz mask) sizes are industry standards, so chip designs can be shared between foundries and fabs, and reticle designs can be put into different photolithography tools. In reality, ASML is the only supplier of EUV photo-tools, so they, more or less, determine the standard reticle size. Any fab using ASML EUV tools all use the same reticle size, and therefore all have the same die-size limits. 1/x
@atpfm The EUV reticles are 104x132mm (about 4x5"), which can project a "field size" (die size on the wafer) of 33x26mm. That's where the 858 sq-mm max die-size comes from. So, all "monolith" chips on the modern EUV processes have to be 858sqmm or less. Any chips over that size have to be made of multiple physical dies, with die-to-die interfaces, or mounted on Silicon interposers, etc. But, the ideal is typically to make monolithic chips whenever possible. 2/x
@atpfm All of TSMCs N3* lines are on standard EUV (as are Intel's processes from 3T, 20A and 18A). The upcoming N2 line (which will be built on a fundamentally different type of transistor construction - switching from FinFETs to Nanosheet / Gate-all-around, plus other advances like backside power delivery) will also be standard EUV. 3/x
@atpfm So there will be a couple more generations, including a couple transistor shrinks, using using the EUV reticles, with the 858sqmm die limit. With the additional transistor shrinks afforded by N2, the transistor count and performance will continue to increase. 4/x
@atpfm But, after TSMC's N2 and Intel's 18A processes, the plan is to move to "High-NA EUV". This will allow continued transistor shrinks, but at a huge cost... High-NA EUV will use the same 104x132mm reticle as EUV, but the field size (the max die size) will be cut in half, to 16.5x26mm, or 429 sqmm. 5/x
@atpfm This will massively limit transistors per chip, even with the smaller transistors afforded by High-NA EUV. It will be very, very interesting to see how high-end chips, which are near the size limit on EUV, manage the transition to High-NA EUV. 6/x
@atpfm Will the smaller transistors (and tighter layout afforded by backside power delivery and other layout optimizations) make it worthwhile to create dies smaller than 429 sqmm? Or will this just increase the amount of multi-die packages with interposers, interfaces, etc?
Asianometry has outstanding videos about EUV and all of this stuff
https://youtu.be/en7hhFJBrAI?si=p7RvFeU44ApkRcTS&t=512
7/7
@joelion TSMC will have backside power delivery too? I thought that was just Intel.
@siracusa I think Intel is pioneering it, but all the cutting edge fab are going to have to do it eventually if they want to keep up with each other.
Their roadmap says N2 will get the Gate All Around / Nanosheet transistors. Then N2P will add backside power. Backside power adds so many steps to the fab process… it will be fascinating to see how much die size it saves